Intellectual Property (IP): DSP |
Application Notes |
AN648: Multioutput Scaler Reference Design |
AN646: 4K Format Conversion Reference Design |
AN 642: 2.5G Reed-Solomon II MegaCore Function Reference Design |
AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications |
AN 623: Using the DSP Builder Advanced Blockset to Implement Resampling Filters |
AN 581: High Definition Video Reference Design (V2) |
AN 559: High Definition Video Reference Design (V1) |
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset |
AN 542: High Definition Video Monitoring Reference Design (M5) |
AN 524: High Definition Video Monitoring Reference Design (M4) |
AN 505: 3GPP LTE Turbo Reference Design |
AN 482: High Definition Video Monitoring Reference Design (M2) |
AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x |
AN 376: Cyclone II Filtering Lab |
AN 375: Cyclone II FFT Co-Processor Reference Design |
AN 362: Stratix II Filtering Lab |
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices |
AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices |
AN 317: Turbo Encoder Co-processor Reference Design |
AN 245: Filtering Reference Design Lab |
User Guides |
BCH IP Core User Guide |
CIC IP Core User Guide |
FFT IP Core User Guide |
FIR II IP Core User Guide |
High Speed Reed-Solomon IP Core User Guide |
LDPC IP Core User Guide |
NCO IP Core Core User Guide |
Reed-Solomon II IP Core User Guide |
Turbo IP Core User Guide |
Viterbi IP Core User Guide |
White Papers |
FPGA vs. DSP Design Reliability and Maintenance |
Hardware in the Loop from the MATLAB/Simulink Environment |
Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology |
Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors |
Increase Performance in Imaging Applications by Integrating DSP Functions With FPGAs |
Introduction to Single Event Upsets |
JESD204A for Wireless Base Station and Radar Systems
(NXP Semiconductors) |
Radar Processing: FPGAs or GPUs? |
Understanding Single Event Functional Interrupts in FPGA Designs |
Versatile Digital QAM Modulator |
Release Notes |
Intel IP Release Notes
|
DSP Builder Release Notes |