Intel provides a range of solutions for synchronous digital hierarchy (SDH) and SONET protocols. The solutions enable simple and fast protocol implementation, reducing design risk, shortening development times, and allowing you to concentrate on the core functions of your system design.
By utilizing built-in transceivers to implement SDH/SONET and other protocols, Stratix® V FPGAs, Stratix IV FPGAs, Stratix II FPGAs, Cyclone® V FPGAs, Cyclone IV FPGAs, Arria® V FPGAs, and Arria II GX FPGAs provide a fully integrated SDH/SONET solution for multi-rate applications including chip-to-chip, backplane, and line-side interfacing. Table 1 provides an overview of the complete SDH/SONET solution.
Stratix II GX, Stratix IV GX/GT SDH/SONET Line-Side Characterization Compliance Report outlining:
Tx jitter tolerance
Tx jitter generation
Rx jitter tolerance
Available from your local Intel® sales representative
External Transceiver Solutions
Use high-density Stratix V, Stratix IV, Stratix III, or Stratix II FPGAs with an external transceiver (or PHY device) in applications requiring the highest density and performance.
SONET/SDH-based protocols are commonly used for backplane connectivity in networking systems. They allow you to reuse pre-defined standards of the SONET/SDH specifications such as framing, scrambling, and error detection. This helps reduce the overall system definition and design complexity. SONET/SDH backplanes tend to be deployed in two styles: distributed switch fabric (see Figure 1) and centralized switch fabric (see Figure 2). Centralized switch fabric relies on dedicated switch cards, while distributed switch fabric implements the switching functionality on the line card. Altera provides solutions for both implementations. Figures 1 and 2 show the difference between the two types of switch fabric.
Intel provides a complete solution for implementing SONET/SDH over a backplane. Stratix V, Stratix IV, Stratix II, Stratix, Arria V, and Arria II GX FPGAs offer transceivers capable of supporting data rates up to OC-192 (10 Gbps) using a single channel. Dedicated features—such as A1A2 pattern detectors and word aligners—are implemented within the transceiver core to reduce the amount of FPGA fabric required to support the protocol. The flexible phase-locked loop (PLL) structure ensures that all data rates can be achieved from a single clock source.