The LVDS I/Os in the Intel® Stratix® 10, Intel Arria® 10, Stratix V, Stratix IV, Stratix III, Arria V, Arria II GX (fast speed grade), Intel Cyclone 10 GX and LP FPGAs allow you to easily implement the Serial Gigabit Media Independent Interface (SGMII) for 10/100/1000 Mb or Gigabit Ethernet. These devices have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS interfaces at data rates up to 1.4 Gbps. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for the SGMII interface at 1.25 Gbps. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device.
The integrated gigabit serial transceivers in Intel Stratix 10, Intel Arria 10, Stratix V, Stratix IV, Stratix II GX, Arria series, Intel Cyclone 10 GX, Cyclone V GX, Cyclone V GT, and Cyclone IV GX also support the SGMII interface.
A typical chip-to-chip SGMII application can use between 12 to 48 full-duplex SGMII for 10/100/1000 Mbps Ethernet or Gigabit Ethernet links. For applications with SGMII links, the LVDS I/Os offer a preferred solution with low-power differential signaling capability compared to transceiver based SGMII implementations.
Figure 1 shows examples of a Gigabit Ethernet line card design consisting of the Intel FPGA Triple-Speed Ethernet Intel FPGA IP function connected by SGMII either to a backplane or through a PHY device to a 10/100/1000 Mbps Ethernet network or backplane. These two examples show that both LVDS I/O and serial transceivers in different Intel FPGA devices can be used to realize SGMII.