HyperTransport™ Technology

HyperTransport™ technology is a high-speed protocol for use in connecting peripherals to computers, mobile computers, servers, communication systems, network equipment, and embedded equipment. It provides up to 128 Gbps aggregate bandwidth, and can be configured with 2, 4, 8, 16, or 32 bit buses. It is intended to bridge any of a variety of processors to the peripherals that may connect to them. It helps reduce the number of buses in the system, and can make multi-processing systems more scalable. It is software-compatible with existing PCI™ applications.

Figure 1. HyperTransport™ Topology

Intel® FPGAs support the HyperTransport core protocol in Intel Arria® and Intel Stratix® devices, including some transceiver variants. 

Stratix V GX FPGAs and Stratix IV GX FPGAs include dedicated circuitry to allow support for HyperTransport 1.0 and 3.0 standards, at data rates up to 3.2 Gbps and bus widths up to 16 bits.

Characterization Report

  • Characterization Reports are available upon request. Contact your local Intel FAE. 

Protocol Standard