The System in the Loop tool enables you to run your FPGA design in real time from a MATLAB environment. The ability to operate in real time can be critical for algorithms with high-processing rates. Traditional MATLAB simulations for such algorithms can incur long computational delays. The System in the Loop tool that is packaged with the DSP Builder for Intel® FPGAs tools, allows you to accelerate complex, high-rate fixed- or floating-point digital signal processing (DSP) in FPGA hardware. This tool also enables you to control, debug, visualize, and verify your FPGA designs—all within the MATLAB environment.
An application programming interface (API), used by the MATLAB software running on your computer to communicate with the FPGA board, allows data to be processed in real time by the FPGA hardware rather than by the MATLAB software. The parameters and stimuli data are passed from the MATLAB workspace to the FPGA, and the FPGA hardware results are read back by the MATLAB software for further analysis and display.
Figure 1 shows an example of MATLAB visualization in radar and beamforming processing.
Figure 1. MATLAB Visualization in Radar and Beamforming Processing
FPGA Verification Within MATLAB Using Intel’s System-Level Debugging Tools
System in the Loop is part of Intel's system-level debugging tool portfolio, which includes the Transceiver Toolkit, External Memory Interface Toolkit, as well as more generic tools, such as System Console and the Platform Designer (formerly Qsys). The Platform Designer (formerly Qsys) uses the Avalon® Memory-Mapped (Avalon-MM) or Avalon Streaming (Avalon-ST) interfaces to build networks in a variety of topologies and hierarchies.
System Console is a tool that can be used to monitor and instrument an FPGA design. It can be used to check clocking operations or reset networks. It can also do more sophisticated tasks, such as drive specific memory-mapped access patterns and check responses. It is useful for both board bring up as well as production test automation. You can create interactive dashboards for a specific task, as shown in Figure 2.
Figure 2. System Console Dashboard
System Console can also perform low-level hardware debugging for any Platform Designer (formerly Qsys). The MATLAB API permits access to function calls using System Console, which in turn provides access to the FPGA hardware. Five simple MATLAB commands are used to refresh, open, read, write, and close a communication channel between the MATLAB design and the FPGA hardware.
The hardware interface to the FPGA can be connected through a legacy JTAG interface or a USB 2.0 interface, as shown in Figure 3. The USB Debug Master provides speeds up to 480 Mbps, permitting high rates of accelerated processing in FPGA hardware. Figure 4 shows that you can easily connect the JTAG or USB signals to the device under test (DUT) using the Platform Designer (formerly Qsys).
Figure 3. MATLAB to FPGA Hardware Protocol Stack
Figure 4. JTAG and USB Debug Master Access
In Figure 5, the DSP Builder for Intel FPGAs (Advanced Blockset) is used to create the FPGA design. This tool creates high-quality fixed- and floating-point register transfer level (RTL) codes, with fMAX and resource usage on par with highly optimized hand-coded hardware description language (HDL). You can also design in traditional Verilog or VHDL, and then add the Avalon® interface ports onto the interfaces to connect your design through the Platform Designer (formerly Qsys).
Figure 5. Connection of FPGA Design to JTAG or USB Debug Master
All FPGA resources can be connected using the Platform Designer (formerly Qsys), and the FPGA design is added as a Platform Designer (formerly Qsys) component. See Figure 6.
Figure 6. Design Platform Diagram
Both the input and output data are buffered on the chip, allowing the FPGA hardware to run at full system speed over the buffered data. The interfaces shown in Figure 7 are Avalon-ST interfaces.
Figure 7. Top-Level FPGA DUT
The input buffer system is shown in Figure 8. Note that the register uses triggers to write addresses as the data is loaded using the MATLAB write command. The output buffer system is similar to the input buffer system.
Figure 8. System in the Loop Input Data Buffer
After that, the Design Platform is added to the Intel Quartus® Prime software project and the design is compiled, as shown in Figure 9.
Figure 9. Adding Platform Designer to Quartus Prime Software Project
Finally, the FPGA is programed with the compiled design. You can now control the entire system through MATLAB commands, as shown in Figure 10:
Figure 10. Control FPGA System via MATLAB
To make it even easier for you to verify your FPGA designs, ready-to-go System in the Loop design templates are available for various Intel FPGA developments boards, such those with Stratix® IV, Stratix V, and Cyclone® V FPGAs.