UDPSDR-HF2 100kHz - 55MHz Receiver Board
Board Image
Block Diagram
Overview
The UDPSDR-HF2 features a 16-bit ADC sampling at 122.88Msps. The HF2 is designed to be a front-end companion to the Intel® FPGA BeMicroSDK from Arrow Electronics. Together, the HF2 and BeMicroSDK form a complete high-performance 100kHz ? 55MHz Digital Down Conversion receiver. The high-performance UDPSDR-HF2 joins the UDPSDR-HF1 (14-bits@80Msps) receiver and the UDPSDR-TX2 transmitter (14-bits@210Msps) to round out the SDRstick family.
Development Kit Software Contents
- BeMicroSDK FPGA image for HDSDR, HPSDR, SDR# and GNU Radio
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-29-5804482205-udpsdr-hf2-users-manual-v3-5.pdf | UDPSDR-HF2 Users Manual | 3.5 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 15.1 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | N |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 0 |
| Parts per Million (PPM) | 0 |
| Board Policy | |
| Return Material Authorization (RMA) Policy | Contact info@zpci.com for RMA. Authorization required for returns. |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. Board is CE compliant but has not been tested. It is a piece of test equipment. |
| Conflict Mineral Policy Compliant |
N |
| Test Plan Summary | |
|
FPGA image for BeMicroSDK to implement a complete 100kHz - 55MHz SDR receiver for use with HDSDR, PowerSDR, SDR# and GNU Radio software. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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