From TES Electronic Solutions GmbH

Request Evaluation

Documentation

Warping Engine

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

TES Warping Engine (http://tes-dst.com/tes-dst/index.php/graphics-rendering/warping-engine?innerpage_style=1) is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory. Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Intel® Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).

Features

Flexible color formats
Arbitrary mapping based on a output->input look-up table per pixel
Easy configuration via registers (less than 20 functional registers)
Highly-efficient compression algorithm for the mapping LUT
High-quality bilinear filtering applying 16x16 sub-pixel positions

Device Utilization and Performance

~7k LEs

Getting Started

The Warping Engine is included in the free-of-charge TES D/AVE HD evaluation kit: http://tes-dst.com/tes-dst/index.php/graphics-rendering/warping-engine?innerpage_style=1 (registration required).

IP Quality Metrics

Basic
Year IP was first released	2013
Latest version of Quartus supported	13.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	N
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Tool to generate Look Up Table and example source code
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	Y
Driver OS support	bare metal, Linux
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modeltech ModelSim, Cadence NCSim
Hardware validated	Y. Altera Board Name VEEK-MT, VEEK-MT C5 SoC
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

Find more DSN members

Find more DSN IP

Find more DSN boards