Warping Engine
Block Diagram
Overview
TES Warping Engine (http://tes-dst.com/tes-dst/index.php/graphics-rendering/warping-engine?innerpage_style=1) is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory. Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Intel® Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2013 |
Latest version of Quartus supported | 13.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | N |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Tool to generate Look Up Table and example source code |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | bare metal, Linux |
Implementation | |
User Interface | AXI; Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modeltech ModelSim, Cadence NCSim |
Hardware validated | Y. Altera Board Name VEEK-MT, VEEK-MT C5 SoC |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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