Terasic Stratix 10 DE10-Pro FPGA Development Kit
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Overview
Terasic DE10-Pro Stratix 10 GX/SX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 3/4-length form-factor package, the DE10-Pro is designed for the most demanding high-end applications, empowered with the top-of-the-line Intel Stratix 10 GX/SX, delivering the best system-level integration and flexibility in the industry. The Stratix 10 GX/SX FPGA features integrated transceivers that transfer at a maximum of 28 Gbps, allowing the DE10-Pro to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 100G/40G QSFP28 modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE10-Pro The Stratix 10 GX FPGA features integrated transceivers that transfer at a maximum of 28 Gbps, allowing the DE10-Pro to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 100G QSFP28 modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE10-Pro provides 4 independent banks of DDR4 SO-DIMM RAM modules and high-speed parallel flash memory. (The sockets can work with Terasic's QDRII or QDR-IV memory modules). The feature-set of the DE10-Pro fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.
Development Kit Hardware Contents
- FPGA Fabric Speed Grade: -2/ Transceiver Speed Grade : -1; Full-height, 3/4-length form-factor package
- Ultra-low-latency, straight connections to 4 external 100G QSFP28 modules; Supported Memory Modules for DDR4-2666/2400;QDRII+550 MHz 144 MBits
- 4 independent banks of DDR4 SO-DIMM sockets with ECC, up to 8 GB 1200MHz for each socket. (Can be paired flexibly with Terasic’s 576-Mbit QDR-II+ or 1
- High-speed parallel flash memory; PCIe Gen3x16 (includes PCIe drivers); Support Intel FPGA OpenCL BSP; 2x5 Timing Expansion Header for 1PPS
- On-board USB Blaster II or JTAG header for FPGA programming; Avalon-ST (AVST x8) configuration via Max II CPLD and CFI flash memory
Development Kit Software Contents
- DE10-Pro Net System Builder
- BSP (Board Support Package) for Intel SDK OpenCL
- Schematic and mechanical drawing
- Memory & PCIe reference design
- Flash and oscillator programming
Support Document
File Name | Description | Version |
---|---|---|
doc-us-dsnbk-42-3703551010380-de10-pro-user-manual-sm.pdf | DE10-Pro User Manual | 1.0 |
Board Quality Metrics
Basic |
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Latest version of Quartus supported | 17.0 |
Required Collateral Available | |
User Guide | Y |
Board Schematics | Y |
Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
Parts per Million (PPM) | N/A |
Board Policy | |
Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
Compliance | |
RoHS Compliant | Y |
CE Compliant | N. N/A |
Conflict Mineral Policy Compliant |
Y |
Test Plan Summary | |
Reference Designs from System CD for customers to access all the peripherals on board. |
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Additional Compliance | |
ISO 9000 & 9001 |
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