Stratix V GX Device Family - TR5-Lite FPGA Development Kit
Board Image
Block Diagram
Overview
The TR5-Lite Stratix® V FPGA Development Kit a slim form-factor PCIe board that features maximum power in a minimum size. Perfect for 1U chassis servers and other stringent environments, the TR5-Lite includes high speed SFP+ interfaces and high-bandwidth memory architecture for high performance computing, cloud systems, and ultra low-latency trading.
Development Kit Software Contents
- TR5-Lite System Builder- create an Intel® Quartus® Prime II project with top-level design file, pin assignments, and I/O standard settings automatically.
- Memory Reference Design
- Schematic and Mechanical Drawing
- Flash and Oscillator Programming
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-42-1404392203-tr5-lite-user-manual.pdf | TR5-Lite User Manual | 1.0 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 13.1 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | Y |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 625 |
| Parts per Million (PPM) | 9531 |
| Board Policy | |
| Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. N/A |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Reference Designs from System CD for customers to access all the peripherals on board. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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