Stratix V GX Device Family - TR5-F40W FPGA Development Kit
Board Image
Block Diagram
Overview
The Terasic TR5-F40W Stratix® V GX FPGA Development Kit provides the ideal hardware platform for developing high-performance and high-bandwidth application. With a standard-height, half-length form-factor package, the TR5-F40W is designed for the most demanding high-end applications, empowered with the top-of-the-line Intel® Stratix V GX, delivering the best system-level integration and flexibility in the industry. The Stratix® V GX FPGA features 340K logic elements and integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the TR5-F40W to be fully compliant with version 3.0 of SATA, version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 10G SFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. An HSMC expansion port also allows users to connect custom daughter cards such as those found on cards.terasic.com. The feature-set of the TR5-F40W fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.
Development Kit Software Contents
- TR5-F40W System Builder - create an Intel® Quartus® Prime II project with top-level design file, pin assignments, and I/O standard settings automatically.
- Memory Reference Design
- Schematic and Mechanical Drawing
- Flash and Oscillator Programming
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-42-3904442203-tr5-f40w-user-manual.pdf | TR5-F40W User Manual | 1.0 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 14.0 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | Y |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 700 |
| Parts per Million (PPM) | 55555 |
| Board Policy | |
| Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. N/A |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Reference Designs from System CD for customers to access all the peripherals on board. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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