Stratix V GX Device Family - DE5-Net FPGA Development Kit
Board Image
Block Diagram
Overview
The Terasic DE5-Net Stratix® V GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 3/4-length form-factor package, the DE5-Net is designed for the most demanding high-end applications, empowered with the top-of-the-line Intel® Stratix V GX, delivering the best system-level integration and flexibility in the industry.The Stratix� V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the DE5-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 10G SFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE5-Net delivers with two independent banks of DDR3 SO-DIMM RAM, four independent banks of Cypress QDRII+ SRAM or functional compatible SRAMS provided by GSI and ISSI, high-speed parallel flash memory, and four SATA ports. The feature-set of the DE5-Net fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.
Development Kit Hardware Contents
- PCI Express (PCIe)x8 edge connector (Includes Windows PCIe drivers)
- Two Independent DDR3 SODIMM Socket, Up to 8GB 800 MHz or 4GB 1066 MHz for each socket
- Four SFP+ connectors plus One RS422 expansion header
- On-Board USB Blaster II or JTAG header for FPGA programming
- Four Independent 550MHz SRAM, 18-bits data bus and 72Mbit for each
Development Kit Software Contents
- DE5-Net System Builder
- Schematic and Mechanical Drawing
- Flash and Oscillator Programming
- BSP (Board Support Package) for Intel® FPGA SDK OpenCL
- Memory & PCIe Reference Design
Support Document
| File Name | Description | Version |
|---|---|---|
| DE5-Net-User Manual | 1 | us |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 13.0 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | Y |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 938 |
| Parts per Million (PPM) | 9685 |
| Board Policy | |
| Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you've received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. N/A |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Reference Designs from System CD for customers to access all the peripherals on board. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.