Max 10 Device Family - DE10-Lite Board
Board Image
Block Diagram
Overview
Terasic DE10-Lite is a cost-effective Intel® MAX® 10 based FPGA board. The board utilizes the maximum capacity MAX 10 FPGA, which has around 50K logic elements(LEs) and on-die analog-to-digital converter (ADC). It features on-board USB-Blaster, SDRAM, accelerometer, VGA output, 2x20 GPIO expansion connector, and an Arduino UNO R3 expansion connector in a compact size. The kit provides the perfect system-level prototyping solution for industrial, automotive, consumer, and many other market applications.The DE10-Lite kit also contains lots of reference designs and software utilities for users to easily develop their applications based on these design resources.
Development Kit Software Contents
- DE10-Lite Control Panel
- DE10-Lite System Builder
- Schematic and Mechanical Drawing
- Memory Design
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-42-2912030810549-de10-lite-user-manual.pdf | DE10-Lite User Manual | 1.3 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 15.1 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | Y |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
| Parts per Million (PPM) | N/A |
| Board Policy | |
| Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you've received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. N/A |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Reference Designs from System CD for customers to access all the peripherals on board. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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