Heterogeneous Extensible Robot Open Platform (HERO)

The traditional FPGA programming has proved problematic to most software engineers, yet the HERO platform provides a solution for everyone. In addition to the traditional professional programming model, the HERO platform’s customized BSP (Board Support Package) also supports OpenCL-based flow development, providing a friendly programming interface for a wide range of algorithms and software programming for software engineers. For a customized system to support OpenCL flow, it requires FPGA hardware to provide complete data and control paths other than compatible software from the host. The OpenCL kernel can then be loaded dynamically in real time and run on the FPGA platform. To support OpenCL Flow, the full FPGA board support package has been ported to the HERO platform and is available as an integral part of the HERO SDK. The FPGA logic part of the existing HERO SDK BSP mainly includes a high-speed communication interface PCIe IP core, a memory DMA controller, an off-chip high-speed memory DDR4 interface, and a communication interface with the FPGA internal module. If users want to increase the speed of communications between the FPGA and the external interface, the HERO platform also has a corresponding BSP reference design that guides customers to implement a variety of flexible external interfaces for better and faster communication. The HERO platform has broad application prospects. Take the service robot as an example, its main role is to help people complete tasks and actions. To achieve this goal, R&D engineers need to implement a variety of complex applications on the robot, including vision, positioning, motion, and grabbing. FPGAs can be of great value in these critical applications, making the processing of complex algorithms efficient and real-time, giving users a good experience.

• Intel Arria 10 GX FPGA; 256MB Flash; 2GB DDR4-2400 x64; On-Board USB Blaster II or JTAG Header for FPGA programming;
• Fast Passive Parallelx32 configuration via Max II CPLD and flash memory; PCIe x8 Edge Connector; USB 3.0 Host/Device; Gigabit Ethernet; UART; CAN;
• SPI; I2C; 8 LEDs; 3 Push-buttons; 8 DIP Switches; 50/100/125MHz Fixed Clock; Programmable Clock Generator; Temperature Sensor; Power Monitor
• Intel CoreTM Processor; RAID configuration 256GB; 8GB-2400 Memory; HDMI 2.0a; USB-C (DP1.2); Integrated LAN: 10/100/1000
• Intel Wireless-AC 8265 + Bluetooth 4.2; USB 3.0 configuration: two host ports; USB type-C configuration: support Thunderbolt 3 (40Gbps) USB 3.1 Gen 2

• Linus Ubuntu 16.04; Intel FPGA Runtime for OpenCLTM Linux x86-64; Intel OpenVINO Toolkit with FPGA Support
• BSP (Board Support Package)

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