HAN Pilot Platform
Board Image
Block Diagram
Overview
The HAN Pilot Platform Development Kit provides users a combination of ARM software and FPGA hardware development platforms. It has a vast memory device and peripherals on the hardware. This kit also includes resourceful reference designs to help users to accomplish their design needs. The hardware offers in the HAN Pilot Platform has the maximum capacity with 660K LEs in Arria 10 SoC FPGA and features various types of advanced multimedia interface such as: HDMI, DisplayPort, and 12G-SDI and a large capacity of DDR4 memory. The board’s high speed network interfaces, Gigabit Ethernet and 10GbE via SFP+ ports, provides hardware resources for applications related to network communication. The pre-installed 4GB DDR4 SO-DIMM module connected to the FPGA can be replaced and expanded up to 8GB in additon to the onboard 1GB DDR4 memory module. Alternatively, this SO-DIMM socket can be used to connect Terasic QDR memory module to the FPGA for low latency applications. The High Pin Count FMC interface onboard is ideal for exploring the variety of functions through add-on daughter cards. The USB Type-C interface introduced for the first time is revolutionary and it offers USB 3.0 and DisplayPort connectivity, as well as bi-directional power delivery between the platform and host PC. The PCIe cabling socket at Gen 3 x4 can be connected to the host PC with Terasic PCIe x4 Cable Adapter (PCA) and PCIe cable to maximize the data transfer rate at lightening speed.
Development Kit Hardware Contents
- Arria 10 SoC FPGA with Dual-Core ARM Cortex A9 1.5GHz CPU and 660K FPGA logic elements
- Support DDR4 SO_DIMM socket (support ECC) and 1GB On-board DDR4 memery chips
- USB Type-C Interface for Display port TX and USB 3.0 application
- High Pin Count FMC Connector and support adjustable VCCIO voltage
- Support HDMI / Ethernet / PCIe interface and 4 SFP+ interface provide 40Gbps throughput
Development Kit Software Contents
- HAN System Builder
- BSP (Board Support Package) for Linux BSP
- BSP 19.1 for Altera SDK OpenCL
- Schematic and Mechanical Drawing
- Memory & PCIe Reference Design
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-42-2307032803217-han-pilot-platform-hardware-manual.pdf | HAN_Pilot_Platform_Hardware_Manual | 1.0 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 18.0 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | Y |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
| Parts per Million (PPM) | N/A |
| Board Policy | |
| Return Material Authorization (RMA) Policy | If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. N/A |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Reference Designs from System CD for customers to access all the peripherals on board. |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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