Cyclone V SoC high-speed ADC Development Kit (ADC-CoC)

From Terasic Inc.

Board Image

Block Diagram

Board Category: Development Kit

Components & Interface: Converter: AD; Expansion: Generic; Industry Standard: Ethernet, USB Device

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Technology: DSP, Embedded Design, General Purpose

Cyclone Series: Cyclone® V: Cyclone® V SE

Board Feature: General User IO: LED, Push Button, Slider Switch


The ADC-SoC is a SoC FPGA motherboard with dual-channel high-speed ADC. The main card is based on the Terasic DE0-Nano-SoC board with a built-in high-speed ADC circuit on the DCC (AD / DA Data Conversion Card) on top of the main card. This feature makes the board an ideal platform for systems that require high-speed ADC applications. The built-in ADC circuit uses SMA as the input interface. The circuit provides two channels, each with 14-bit resolution and a sample rate of up to 150 MSPS (Megasamples per Second).

Order Information

Ordering Code
P0435$550.00Buy Now

Development Kit Hardware Contents

  • Cyclone® V SoC FPGA with ARM Cortex-A9 Dual-Core; USB Blaster II; Three 50MHz clock sources from the clock generator
  • Arduino Expansion Header (Uno R3 compatibility), can connect with Arduino shields; Two 14-bit AD Converters with 150 MSPS
  • 2 Push Buttons; 4 Slide Switches; 8 Green User LEDs; Three 50MHz Clock Sources from the Clock Generator; A/D Converter, 10-pin Analog input
  • 1 GB DDR3 SDRAM; 1 Gigabit Ethernet PHY with RJ45 connector; USB OTG Port, USB Micro-AB connector; Micro SD Card Socket
  • Accelerometer; UART to USB, USB Mini-B Connector; Warm and Cold Reset Buttons; On-Board RTC; LTC 2x7 Expansion Header

Development Kit Software Contents

  • Schematic and Mechanical Drawing
  • ADC-SoC Control Panel - access various peripherals on the FPGA board from a host computer
  • ADC-SoC System Builder - create an Intel® Quartus® Prime II project with top-level design file, pin assignments, and I/O standard settings automatically
  • Memory Reference Design

Support Document

File Name
doc-us-dsnbk-42-2108361005542-adc-soc-user-manual-dsn.pdfADC-SoC User Manual1.0

Board Quality Metrics

Latest version of Quartus supported 16.1
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

Parts per Million (PPM)
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to us within 7 days after you've received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit:
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Test Plan Summary

Reference Designs from System CD for customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

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