Arria 10 GX Terasic TR10a-HL2

The Terasic TR10a-HL2 Arria 10 GX FPGA Dev. Kit provides the robust hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. Powered by the top-of-the-line Intel Arria 10 GX, the full-height, half-length accelerator aims at delivering the best system-level integration and flexibility to the industry. The Arria® 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the TR10a-HL2 to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 40G QSFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the TR10a-HL2 delivers with six independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-set of the TR10a-HL2 fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing. The TR10a-HL2 has a PCIe x16 edge connector which includes two PCIe Gen3 x8 interfaces. Each interface is directly connected to the FPGA PCIe Hard IP. It allows one PCIe Gen3 x8 connection in standard PCIe slot or two PCIe Gen3 x8 connections in a PCIe bifurcation slot. With dual PCIe Gen3 x8 interfaces, the TR10a-HL2 board can provide double the throughput rate than that of the TR10a-HL board.

• 1,150K LEs; 67-Mbits embedded memory; 48 (12.5Gbps) transceivers; 128MB Flash; 6 Independent 550 MHz QDRII+SRAMs; 18-bits data bus
• Onboard USB Blaster II or JTAG header for FPGA Programming; FFPx16 Configuration via Max II CPLD and flash memory; 48MB QDRII+ SRAM
• PCI Express 6-pin power connector, 12V DC Input; PCI Express Edge connector power; PCI Express standard height and 1/2-length
• Four QSFP+ connectors; PCIex16 edge connector (includes dual PCIE gen3 x8 interfaces); 2x5 RS422 expansion header; 2x4 GPIO expansion header
• 8 LEDs; 4 push-buttons; 2 dip switches; 50MHz Oscillator; Temperature sensor; Fan control; Power monitor

• TR10a-HL2 System Builder
• BSP (Board Support Package) for Altera SDK OpenCL
• Schematic and Mechanical Drawing
• Memory & PCIe Reference Design
• Flash and Oscillator Programming

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