From System Level Solutions, Inc.

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Documentation

USB 2.0 On-The-Go (USB20OTG)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria® V, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. It supports both USB Host and USB Device peripheral functionality. While acting as USB Host, it supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes. While acting as USB Device peripheral, it supports High Speed (HS) and Full Speed (FS) modes.IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Intel® Platform Designer (formerly Qsys) Ready component and hence can be easily integrated in Platform Designer system.

Features

Supports UTMI + Low Pin interface (ULPI) interface
Supports Asynchronous Avalon clock interface
Configurable memory depth, Supports software controlled PHY register access
Configurable to use as HOST only mode or DEVICE only mode
Ready to use component for Qsys, Meets Intel® Design Assistant guidelines

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/communication/usb-2-0-on-the-go-usb20otg.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/145.htmlFor any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released	2014
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Windows and Linux driver and sample application file, Nios II HAL object and sample application file
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	Y
Driver OS support	Windows, Linux
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Altera ModelSim
Hardware validated	Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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