USB 2.0 HUB (USB20HUB)
Block Diagram

Features
- Configurable Transaction Translator buffers, Supports connect/disconnect detection of down-stream ports
- Supports High speed, Full speed and Low speed peripheral devices
- Supports standard as well as hub class-specific requests, Reliable, Easy to Use
- Remote wakeup capable, Configurable Hub speed, Supports Suspend and Resume
- Integrated Transaction Translator (TT), Supports individual port power switching
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel® Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/146.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2014 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | Y |
Driver OS support | Windows, Linux |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Altera ModelSim |
Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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