Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon interface and ULPI interface support. The core supports both High Speed(480 Mbps) and Full Speed(12 Mbps) functionality. The core supports three preconfigured endpoints Control, IN, and OUT. It can be configured for up to 15 IN as well as OUT endpoints on customer's request at additional cost.IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Intel® Platform Designer (formerly Qsys) Ready component and hence can be easily integrated in Platform Designer system.The package includes ModelSim pre-compiled library of Host-BFM with predefined test cases for IP core simulation and verification.
Platform Designer (formerly Qsys) based Encrypted IP Core
Reference Design and Technical Documents
Nios® II HAL Driver (Object Code) and Application Example (C Code)
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/113-usb20sr.htmlFor any question or support, contact at firstname.lastname@example.org.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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