USB 2.0 Device, Software based enumeration, FIFO Interface (USB20SF)
Block Diagram
Overview
The USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon interface and ULPI interface support. The core supports both High Speed (480 Mbps) and Full Speed (12 Mbps) functionality. The core supports three preconfigured endpoints - Control, Bulk IN and Bulk OUT. It can be configured for up to 15 IN/OUT endpoints on customer's request at additional cost. Each configurable endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers.The core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel Quartus® Prime II design software. The package includes ModelSim precompiled library for core simulation and verification.
Features
- Supports both Full-speed (12 Mbps) and High-speed (480 Mbps)
- Supports UTMI + Low Pin interface (ULPI) interface, Supports Control, Bulk and Interrupt transfers
- Software controlled CONTROL endpoint
- Supports Synchronous FIFO Interface for non CONTROL endpoint
- Optimized for use with Intel® Nios® II embedded processor
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/143-usb20sf.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2011 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Nios II HAL Library & Application example, Windows Driver and Application example |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Windows, Linux |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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