USB 1.1 Device, Software based enumeration, RAM Interface (USB11SR)
Block Diagram
Overview
The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface. The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges. The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints. It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoints has an endpoint controller that supports Interrupt, Bulk and Isochronous transfers.The core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel® Quartus® Prime II design sfotware. The package includes ModelSim precompiled library for core simulation and verification.
Device Utilization and Performance
Cyclone® III - 1900 LE, 8 M9K,103MHz, Cyclone IV - 1900 LE, 8 M9K, 109MHz, Cyclone V - 840 ALM, 8 M10K, 60MHz, Stratix® III - 1300 ALUT, 8 M9K, 141MHz, Stratix IV - 1300 ALUT, 8 M9K, 130MHz, Stratix V - 800 ALM, 8 M20K, 100MHz, Arria® II - 1300 ALUT, 8 M9K, 115MHz, Arria V - 830 ALM, 8 M10K, 83MHz, MAX® 10 - 1900 LE, 8 M9K, 104MHz
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/129.html.For any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2003 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Nios II HAL Object Library & Application example, Windows Driver and Application example |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Windows, Linux |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.