SD UHS-II Host Controller
Block Diagram
Overview
SLS's SD UHS-II Host Controller is a ultra high speed, SD 3.0 & UHS-II Addendum v1.02 specification compliant IP that addresses your needs for removable storage in a wide range of applications. IP Core is backward compatible with legacy SD interface and provides connectivity with removable storage media, including all types of SD cards. The SD UHS-II Host interface is based on a standard 32-bit Avalon bus which is used to transfer data and configure the IP, hence allows easy integration for Intel® Platform Designer (formerly Qsys) systems. IP Core can be configured for the multiple device compatibility, various internal buffer sizes, High/low speed range, Full or Half duplex mode, Legacy SD or UHS-II interface selection. The functionality of the IP Core has been verified using Intel® ModelSim and SLS USB3.0 Development Board for it's high speed performance and backward compatibility. The IP Core's register based high performance architecture employs power management techniques, making it ideal for low-power applications
Features
- Supports High Speed interface with data rate up to 156 MB/s for Full Duplex mode and 312 MB/s for 2-Lane Half Duplex mode
- Supports Full Duplex and 2-Lane Half Duplex interface
- Uses SLI30481 PHY chip for Physical layer, Supports 8 bit and 16 bit PHY interface
- Supports Point to Point for Single UHS-II device and Ring topology for supporting Multiple UHS-II devices
- Compliant with UHS-II Addendum v1.02, Compliant with SD 3.0 specification
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel® Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/146.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2015 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Nios II Example Files |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | None |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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