SD/eMMC Host Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria® V, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The SD/eMMC Host Controller IP Core implements the SD Physical Layer v3.0 and eMMC Physical Layer v4.51 compatible Host Controller which supports standard SD Card, SD High Capacity Card (SDHC), SD Extended Capacity Card (SDXC) and eMMC. Fully register based configuration makes it very easy to integrate in wide range of application. The SLS SD/eMMC Host Controller IP Core gives full support for Intel® FPGA's Platform Designer (formerly Qsys) based system and provides communication between Intel FPGA's Avalon Bridge and Secure Digital (SD) Card and eMMC.


  • Supports 1-bit, 4-bit and 8-bit data interface
  • Supports SD Card, SD High Capacity Card (SDHC) and SD Extended Capacity Card (SDXC)
  • Supports CRC7 and CRC16 generation and verification on Hardware
  • Supports SDR12, SDR25, DDR50, DDR interfaces, Supports integrated 32 bit DMA interface
  • Follows SD Physical Layer Specification v3.0 and eMMC Physical Layer Specification v4.51

Device Utilization and Performance


Getting Started

1. Request an Evaluation version with License from An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at any question or support, contact at

IP Quality Metrics

Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II HAL Object File and Sample Application File
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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