I2S Controller
Block Diagram
Overview
I2S Controller is designed to transfer audio data to and from Audio codec. It can be configured as both Master and Slave mode using software. The I2S IP is Phillips Inter IC Sound (I2S) specification compliant core for Intel® FPGA devices.It is provided as Intel® Platform Designer (formerlyl Qsys) ready component and integrates easily into any Platform Designer generated system.
Features
- 8-bit and 16-bit sampling data width support
- Variable sampling rate support, Used in both master/slave mode
- Internal two 64 x 32 bit FIFO for data buffering
- 32-bit DMA engine for both data transmit and receive for reducing CPU overhead
- Transmit and Receive Operation, Compliant with the Avalon bus, Left and Right channel support
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel® Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/121.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2006 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | None |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html, http://www.slscorp.com/products/santac |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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