I2C Slave
Block Diagram
Overview
The I2C slave IP is fully synthesizable core and compatible with Phillips I2C standard. The IP uses I2C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.The I2C Slave IP Core is provided as Intel® Platform Designer (formerly Qsys) ready component and integrates easily into any Platform Designer generated system.
Features
- Interrupt or bit-polling driven byte-by-byte data transfer, Start/Stop detection
- Uses two wires to transfer information between devices, Bi-directional data transfer
- Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
- 7-bit addressing format, Fixed data width of 8 bits, Data transfer in multiples of bytes
- Operates from a wide range of input clock frequency, Fully synthesizable
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/120.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2007 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Nios II Example Files |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | None |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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