I2C Slave

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The I2C slave IP is fully synthesizable core and compatible with Phillips I2C standard. The IP uses I2C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.The I2C Slave IP Core is provided as Intel® Platform Designer (formerly Qsys) ready component and integrates easily into any Platform Designer generated system.

Features

  • Interrupt or bit-polling driven byte-by-byte data transfer, Start/Stop detection
  • Uses two wires to transfer information between devices, Bi-directional data transfer
  • Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
  • 7-bit addressing format, Fixed data width of 8 bits, Data transfer in multiples of bytes
  • Operates from a wide range of input clock frequency, Fully synthesizable

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/interface/i2c-slave.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/120.htmlFor any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Nios II Example Files
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.