I2C Controller
Block Diagram
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Overview
I2C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I2C Controller provides an interface between Nios® II processor and I2C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I2C Controller IP core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode.It is provided as Intel® Platform Designer (formerly Qsys) ready component and integrates easily into any Platform Designer generated system.
Features
- Automatic detection and adoption to bus interface type, Multi-master operation
- Compatible with Philips I2C(PCF 8584) standard, Supports both Master and Slave mode
- Arbitration-lost interrupt with automatic transfer cancellation, Supports 7 bit addressing mode
- Start/Stop/Repeated Start/Acknowledge generation and detection, Operates from wide range of input clock frequencies
- Byte-by-byte data-transfer is driven by Interrupt or Bit-polling, Bus-Busy detection
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel® Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/146.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2006 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Nios II Example Files |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | None |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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