Ethernet MAC 10/100

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

Stratix Series: Stratix® IV, Stratix® V


The Ethernet MAC 10/100 IP is designed for implementation of CSMA/CD in accordance with the IEEE 802.3 and 802.3u standards. The core is a 10/100 Media Access Controller (MAC) for Intel® FPGA devices that supports half and full duplex modes. The core connects to any industry standard ethernet PHY device via MII (Media Independent Interface for 10/100 Mbps applications) and to a user application via the Avalon bus interface.The core has been optimized for popular FPGA devices and its functionality has been verified on the real hardware. It is provided as Intel Quartus® Prime II Mega Function (Intel Platform Designer, formerly Qsys, ready component) and integrates easily into any Qsys generated system using Nios® II Avalon bus.


  • Performs MAC layer function as per IEEE 802.3 and Ethernet standard
  • Collision detection and auto re-transmitting on collision in half duplex mode (CSMA/CD protocol)
  • IEEE 802.3 Media Independent Interface(MII), Complete status for TX/RX packets, 32 bit CRC generation and checking
  • Flow control and generation of control frames in full duplex mode (IEEE 802.3x)
  • Supports full duplex and half duplex modes, Supports 10/100 Mbps speed

Device Utilization and Performance


Getting Started

1. Request an Evaluation version with License from An email send to download the IP Core and the license file to compile theIntel® Quartus PRime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at any question or support, contact at

IP Quality Metrics

Year IP was first released2006
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II example file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportAny
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name,
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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