Technology:Memory Interfaces and Controllers: Flash
Cyclone Series: Cyclone® IV, Cyclone® V
Enhanced ClearNAND Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) standard. Two advanced architectures - register based and descriptor based, provides high speed performance, software flexibility, data integrity and device compatibility. Descriptor based architecture reduces amount of CPU intervention.Enhanced ClearNAND Controller IP Core gives full support for Intel® FPGA's Platform Designer (formerly Qsys) based systems and provides communication between processor and NAND Flash device using Avalon interface.
Supports ONFI EZ NAND 2.3 plus enhanced command set
Supports integrated 32 bit DMA interface for data transfer, Supports interrupt driven functionality
Supports [0-5] asynchronous and [0-5] source synchronous modes of operation
Supports 8 bit data bus, Configurable buffer depth, Multi-Plane (interleave) operation support
Supports command repeat and auto address increment functionality
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/141-enhanced-clearnand-controller.htmlFor any question or support, contact at firstname.lastname@example.org.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Nios II Example Files
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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