Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Inte®l FPGA built-in 10 Gbps transceiver. It isa one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS)and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. Itprovides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the controltransfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
Supports SuperSpeed+ (SSP) and SuperSpeed (SS) modes
Uses Intel FPGA Device Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1
Supports High, Full and Low Speed modes using External USB 2.0 PHY
Simple FIFO interface to transfer data over non-control endpoint. Capable to support up to 31 endpoints
For Intel® Arria® 10 (up to Gen 2 10Gbps Interface) uses ~16244 ALM and ~76 M20K Memory. For Intel® Cyclone® 10 (up to Gen 2 10Gbps Interface) uses ~16395 ALM and ~73 M20K Memory. For Cyclone V (up to Gen 1 5Gbps Interface) uses ~5600 ALM and ~63 M10K Memory.For Arria V (up to Gen 1 5Gbps Interface) uses ~5510 ALM and ~66 M10K Memory.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.htmlFor any question or support, contact at email@example.com.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
ModelSim for Intel FPGA
Y. Altera Board Name Intel Arria10GXKit;Intel Arria10 SoCKit; Intel Cyclone10GX Kit; CycloneV Dev Kit; iWave Arria 10 SOM
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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