Embedded USB 3.0/3.1 Gen1 (eUSB30SF) Device Controller

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria® V, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

USB 3.0/3.1 Gen 1 standard is ubiquitous across the world and has raised the demand to implement it in various products. The integration of USB 3.0/3.1 Gen 1 Device with FPGA development board needs 60+ I/O for USB 3.0/3.1 Gen 1 PHY chip to connect it with FPGA. This adds an extra cost to the board. Intel® has introduce the FPGA which has in built transceiver which run at 5Gbps speed (same as USB 3.1 Gen 1 (USB 3.0) Specification) with features like 8b/10b, SKIP control etc. required during implementing USB 3.0/3.1 Gen 1 Controller. SLS has integrate the USB 3.1 Gen 1 Device IP Core with the Intel Transceiver and USB 2.0 PHY chip, and developed the eUSB 3.1 Gen 1 Device Controller IP Core, offering low cost solution.

Features

  • USB 3.0 compatible link for embedded applications
  • Supports CONTROL, BULK and ISO transfer without stream support
  • Implementation of PHY Layer (with Intel® FPGA 5+ Gbps transceiver), Link Layer and Protocol Layer
  • Supports 32-bit PHY Layer data interface between Intel® FPGA Transceiver PHY IP core and Link Layer

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/communication/usb-30-device/eusb3-0-device-controller-eusb30sf.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel® Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/127.htmlFor any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/eusb30-development-board.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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