AC'97 Controller

Block Diagram

Solution Type: IP Core

End Market: Consumer, Medical

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Avalon compliant AC`97 (Audio Codec) Controller IP core provides an interface between Nios® II processor and AC`97. It supports one AC`97 codec with 6 output and 3 input channels. The core is fully compliant with AC?97 specification Rev.2.1.It is provided as Intel® Platform Designer (formerly Qsys) ready component and integrates easily into any Platform Designer generated system.

Features

  • Variable and fixed sample rate support up 48 KHz
  • Compliant with AC 97, rev 2.1 (LM4550)
  • Stereo input channel support, Mono microphone channel support
  • Supports 6 output channel surround sound
  • 16, 18 and 20 bit sample size support

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/interface/ac97-controller.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/122.htmlFor any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2005
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/santacruz-snap-on-boards/audio-codec.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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