The FPGA IP core supports or can be used as MECHATROLINK-III C1 Master, Slave and Multi-slave functions.
The basic function of the FPGA IP core is equivalent JL-100 and JL-102 communication chip from Yaskawa.
Since the logic circuit on FPGA is programmable, you can add or customize different type of interface and you can incorporate other peripheral circuit to the user interface of the FPGA IP core. This will make your product development faster, flexible and customizable.
Supports MECHATROLINK-Ⅲ C1 Master, Slave and Multi-Slave.
Device Utilization and Performance
Note that this is just a reference value since it varies dependent on options at the time of synthesis and implementation environment.
-\tThe value is from a standalone SYM3A-M. It does not include sample interfaces and other circuits.
-\tIt is the fitting result of Cyclone® V 5CSTFD6D5F31I7 (Sodia evaluation board with FPGA)
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IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: Local Interface
IP-XACT Metadata included
Y. Altera Board Name Mpression Sodia Evaluation Board by Macnica (ALTSODIAC5ST)
Industry standard compliance testing performed
If yes, which test(s)?
If yes, on which Altera device(s)?
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available
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