MECHATROLINK-III Master/Slave (SYM3A)

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Industrial

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Cyclone Series: Cyclone® V, Cyclone® V SoC

Overview

The FPGA IP core supports or can be used as MECHATROLINK-III C1 Master, Slave and Multi-slave functions. The basic function of the FPGA IP core is equivalent JL-100 and JL-102 communication chip from Yaskawa. Since the logic circuit on FPGA is programmable, you can add or customize different type of interface and you can incorporate other peripheral circuit to the user interface of the FPGA IP core. This will make your product development faster, flexible and customizable.

Features

  • Supports MECHATROLINK-Ⅲ C1 Master, Slave and Multi-Slave.

Device Utilization and Performance

Note that this is just a reference value since it varies dependent on options at the time of synthesis and implementation environment. -\tThe value is from a standalone SYM3A-M. It does not include sample interfaces and other circuits. -\tIt is the fitting result of Cyclone® V 5CSTFD6D5F31I7 (Sodia evaluation board with FPGA) Logic(ALMs):8,483 RAM Blocks:62 PLL:1

Getting Started

Please contact us for more information.

IP Quality Metrics

Basic
Year IP was first released2018
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNon
Implementation
User InterfaceOther: Local Interface
IP-XACT Metadata includedN
Verification
Simulators supportedNon support
Hardware validated Y. Altera Board Name Mpression Sodia Evaluation Board by Macnica (ALTSODIAC5ST)
Industry standard compliance testing performed
Y
If yes, which test(s)?MECHATROLINK
If yes, on which Altera device(s)?5CSTFD6D5F31I7N
If Yes, date performed
02/24/2017
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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