CAN/CAN FD IP

Block Diagram

Solution Type: IP Core

End Market: Automotive, Industrial, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The IP supports both traditional CAN and the new CAN FD standard, both in ISO and non-ISO mode. It is delivered with a full bus interface and a memory mapped register bank for control and status. Status and error information can also be embedded in the data stream. The IP can be configured to support multiple CAN channels with a shared receive buffer, for easier integration and to minimize foot print. The IP has full support for DMA offering low latency transfers to the host system. Interrupt rate adaptation is available to minimize system load. All features are build time configurable to enable build size fine tuning. The IP can also be delivered as a super tiny version for minimal foot print, only containing the BSP (bit stream processor) without any buffering or or bus interface. The IP is delivered with full documentation and implementation examples. The IP is 100% compliant to the Bosch reference model and also tested by the independant test house C&S.

Features

  • Small footprint but yet feature rich IP for CAN and CAN FD, fully compliant to ISO 11898-1:2015
  • Multiple channels sharing the same receive buffer
  • Low latency DMA support with interrupt rate adaptation
  • Full memory mapped system bus support, fully buffered receive and transmit channels
  • Many features for CAN bus analysis: 32 and 64 bit timestamps, listen only mode, self listen mode, auto acknowledge mode, single shot mode

Device Utilization and Performance

Supports standard CAN bus speeds between 1 kbit/s to 1Mbit/s and CAN FD data phase bit rates of up to 13.333 Mbit/s at 3 clock cycles per bit with a 40 MHz clock. Device utilization numbers can be found in the documentation.

Getting Started

Contact Synective Labs for further details and evaluation. Phone: +4613461040 Email: sales@synective.se Web: http://www.synective.se/index.php/solutions/ip-for-can-and-can-fd/

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAny supporting Avalon
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Several for example EK-10M08E144 (MAX 10)
Industry standard compliance testing performed
Y
If yes, which test(s)?Bosch reference model
If yes, on which Altera device(s)?Cyclone IV
If Yes, date performed
06/01/2016
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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