Synaptic Laboratories Limited (SLL) OctaBus Memory Controller (OBMC) IP currently supports 4 different PSRAM from JSC. SLL has physically qualified the first two OctaRAM devices from JSC with OBMC IP. Free long term evaluation licenses of S/Labs OBMC IP will be available soon to all Intel customers for use on COTS and proprietary FPGA boards! Please contact S/Labs to participate in our Early Access Program to test JSC OctaRAM in your project today. --- Qualification status as of June 2019. Physically validated: JSC28SSP8AGDY-50I (128 Mbit, 1.8V) and JSC64SSP8AGDY-50I (64 Mbit, 1.8V). Validated in simulator: JSC28SSU8AGDY-75I (128 Mbit, 3.0V) and JSC64SSU8AGDY-75I (64 Mbit, 3.0V).
Synaptic Labs is collaborating with JSC to physical qualify JSC's OctaRAM devices
Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on Cyclone 10 GX, Arria 10, Arria 10 SoC, Stratix 10 and Stratix 10 SoC.
Automatically configures OctaRAM devices at power on, PSRAM immediately available for read/write access without a customer boot loader.
Internal clock-crossing logic to reduce circuit area of customer's design.
Device Utilization and Performance
Starting from around 400 4-to-1 logic elements, SLL's OBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA. Furthermore, x8 OctaRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs. -- Nios II software performance on OctaRAM @ 150 MHz is highly competitive with 16-bit DDR3 @ 333 MHz, and is up to around 1.5x faster than 16-bit SDR SDRAM @ 100 MHz.
Contact email@example.com to participate in our Early Access Program for OctaBus Memory Controller IP with Avalon interface.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Simulation model available for free upon request.
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Nios II HAL
IP-XACT Metadata included
Intel Edition of Modelsim
Y. Altera Board Name A modified Cyclone 10 LP Evaluation Kit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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