OctaBus Memory Controller IP for AP Memory OctaRAM

Block Diagram

Solution Type: Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10

Overview

Synaptic Laboratories Limited (SLL) OctaBus Memory Controller (OBMC) IP currently supports 2 different OctaRAM from AP Memory. SLL has physically qualified the first OctaRAM devices from AP Memory with OBMC IP. Free long term evaluation licenses of S/Labs OBMC IP will be available soon to all Intel customers for use on COTS and proprietary FPGA boards! Please contact S/Labs to participate in our Early Access Program to test AP Memory OctaRAM in your project today. -- Device qualification status as of June 2019. Physical validation: APM6408L-3OC (64 Mbit, 3.0V). Validation in simulation: APM6408L-OC (64 Mbit, 1.8V). Support planned: APS25608L‐OC (512 Mbit, 1.8V) and APS51208L‐OC (512 Mbit, 1.8V).

Features

  • Synaptic Labs is collaborating with AP Memory to physical qualify AP Memory's OctaRAM devices
  • Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on Cyclone 10 GX, Arria 10, Arria 10 SoC, Stratix 10 and Stratix 10 SoC.
  • Automatically configures the OctaRAM devices at power on, PSRAM immediately available for read/write access without a customer boot loader.
  • Internal clock-crossing logic to reduce circuit area of customer's design.

Device Utilization and Performance

Starting from around 400 4-to-1 logic elements, SLL's OBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA. Furthermore, x8 OctaRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs. Nios II software performance on OctaRAM @ 150 MHz is highly competitive with 16-bit DDR3 @ 333 MHz, and is up to around 1.5x faster than 16-bit SDR SDRAM @ 100 MHz.

Getting Started

Contact info@synaptic-labs.com to participate in our Early Access Program for OctaBus Memory Controller IP with Avalon interface.

IP Quality Metrics

Basic
Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Simulation model available for free upon request.
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportNios II HAL
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedIntel Edition of Modelsim
Hardware validated Y. Altera Board Name A modified Cyclone 10 LP Evaluation Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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