Multiple Bus Memory Controller for HyperRAM, OctaRAM, Xccela PSRAM and xSPI PSRAM with support for Hyper Flash, HyperMCP and xSPI Flash
Block Diagram
Overview
Multiple Bus Memory Controller (MBMC) IP supports over 40 different xSPI and xSPI-like PSRAM and xSPI NOR Flash devices from AP Memory, Cypress, ISSI, and JSC. -- SLL collaborates with memory vendors to physically qualify many of their devices. -- MBMC currently supports 1st Gen HyperRAM from Cypress and ISSI, OctaRAM from AP Memory and JSC, and Xccela PSRAM from AP Memory. -- MBMC currently supports 1st Gen HyperFlash and 1st Gen HyperMCP from Cypress and ISSI. -- Contact SLL about availability of xSPI Profile 1.0 NOR Flash support. -- SLL MBMC is based on SLL's HyperBus Memory Controller (HBMC) IP bundled with Intel's Cyclone 10 LP Evaluation Kit. SLL's HBMC IP has been successfully deployed by industrial consortia and high profile scientific research organisations and universities and Fortune Global 500's down to the smallest SME's in commercial and industrial projects and products around the globe, from USA to China.
Features
- Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on Cyclone 10 GX, Arria 10, Arria 10 SoC, Stratix 10 and Stratix 10 SoC.
- Supports xSPI PSRAM from multiple vendors.
- Supports HyperRAM and HyperFlash in the one memory controller instantiation. Supports HyperMCP devices.
- Automatically configures the memory devices at power on, PSRAM and Flash immediately available for read/write access without a customer boot loader.
- Internal clock-crossing logic to reduce circuit area of customer's design.
Device Utilization and Performance
Starting from around 400 4-to-1 logic elements, SLL's MBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA. Furthermore, x8 xSPI PSRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs. -- On Arria 10 SoC, Stratix 10 SoC the 166 MHz DDR HyperFlash provisions around 333 Megabytes/s of wires peed bandwidth which is ~3x faster wire speed bandwidth than the x16 ONFi Flash @ 50 MHz in the HPS. Provision ~3x more bandwidth for Linux flash file systems on ARM cores to accelerate Uboot and Linux performance. -- Nios II software performance on HyperRAM and HyperFlash @ 150 MHz is highly competitive with 16-bit DDR3 @ 333 MHz, and is up to ~1.5x faster than 16-bit SDR SDRAM @ 100 MHz. Execute code directly from HyperFlash at similar levels of performance.
Getting Started
Free long term evaluation licenses of S/Labs MBMC IP with Avalon Interface are available to all Intel customers for use on COTS Development Boards and customer's proprietary boards! -- Get started rapidly with one of our detailed step-by-step tutorials on our website. All tutorials include free trials of our IP.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Simulation model available for free upon request. |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | Nios II HAL |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Intel Edition of Modelsim |
| Hardware validated | Y. Altera Board Name Intel Cyclone 10 LP Evaluation Kit. Devboards HyperMAX 25 and 50. |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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