Multiple Bus Memory Controller for HyperFlash, HyperMCP and xSPI Flash with support for HyperRAM, OctaRAM, Xccela PSRAM and xSPI PSRAM

Block Diagram

Solution Type: Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10


Multiple Bus Memory Controller (MBMC) IP supports over 40 different xSPI NOR Flash and xSPI and xSPI-like PSRAM devices from AP Memory, Cypress, ISSI, and JSC. -- SLL collaborates with memory vendors to physically qualify many of their devices. -- MBMC currently supports 1st Gen HyperFlash and 1st Gen HyperMCP from Cypress and ISSI. -- MBMC currently supports 1st Gen HyperRAM from Cypress and ISSI, OctaRAM from AP Memory and JSC, and Xccela PSRAM from AP Memory. -- Contact us about availability of xSPI Profile 1.0 NOR Flash support. -- SLL MBMC is based on SLL's HyperBus Memory Controller (HBMC) IP bundled with Intel's Cyclone 10 LP Evaluation Kit. SLL's HBMC IP has been successfully deployed by industrial consortia and high profile scientific research organisations and universities and Fortune Global 500's down to the smallest SME's in commercial and industrial projects and products around the globe, from USA to China. 


  • Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on Cyclone 10 GX, Arria 10, Arria 10 SoC, Stratix 10 and Stratix 10 SoC.
  • Supports HyperFlash and HyperRAM in the one memory controller instantiation. Supports HyperMCP devices.
  • Automatically configures the memory devices at power on, Flash and PSRAM immediately available for read/write access without a customer boot loader.
  • Internal clock-crossing logic to reduce circuit area of customer's design.

Device Utilization and Performance

Starting from around 400 4-to-1 logic elements, SLL's high bandwidth MBMC is several times smaller than Intel's low bandwidth QSPI flash controller. -- On Arria 10 SoC, Stratix 10 SoC the 166 MHz DDR HyperFlash provisions around 333 Megabytes/s wire speed bandwidth which is ~3x faster wire speed bandwidth than the x16 ONFi Flash @ 50 MHz in the HPS. Provision ~3x more bandwidth for Linux flash file systems on ARM cores to accelerate Uboot and Linux performance. -- Nios II software performance on HyperRAM @ 150 MHz is highly competitive with 16-bit DDR3 @ 333 MHz, and is up to ~1.5x faster than 16-bit SDR SDRAM @ 100 MHz. HyperFlash performance is similar.

Getting Started

Free long term evaluation licenses of S/Labs MBMC IP with Avalon interface are available to all Intel customers for use on COTS Development Boards and customer's proprietary boards! -- Get started rapidly with one of our detailed step-by-step tutorials on our website . All tutorials include free trials of our IP.

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Simulation model available for free upon request.
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportNios II HAL
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedIntel Edition of Modelsim
Hardware validated Y. Altera Board Name Intel Cyclone 10 LP Evaluation Kit. Devboards HyperMAX 25 and 50.
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.