Synaptic Laboratories Limited (SLL) Hyper Bus Memory Controller (MBMC) IP for 1st Generation HyperFlash, Hyper MCP and HyperRAM has been physically qualified with several Cypress and ISSI devices. -- HBMC currently supports 1st Gen HyperBus devices from Cypress and ISSI. -- A version of SLL's HyperBus Memory Controller (HBMC) IP is bundled with Intel's Cyclone 10 LP Evaluation Kit. SLL's HBMC IP has been successfully deployed by industrial consortia and high profile scientific research organisations and universities and Fortune Global 500's down to the smallest SME's in commercial and industrial projects and products around the globe, from USA to China.
Supports full 166 MHz @ 1.8v and 100 MHz @ 3.0v clock speeds on Cyclone 10 GX, Arria 10, Arria 10 SoC, Stratix 10 and Stratix 10 SoC.
Supports HyperFlash and HyperRAM in the one memory controller instantiation. Supports HyperMCP devices.
Automatically configures the memory devices at power on, Flash and PSRAM immediately available for read/write access without a customer boot loader.
Internal clock-crossing logic to reduce circuit area of customer's design.
Device Utilization and Performance
Starting from around 400 4-to-1 logic elements, SLL's HBMC is at least 2x smaller than any of Intel's QSPI Flash controllers, and offers significantly faster bandwidth. -- On Arria 10 SoC, Stratix 10 SoC the 166 MHz DDR HyperFlash provisions around 333 Megabytes/s of wire speed bandwidth which is ~3x faster wire speed bandwidth than the x16 ONFi Flash @ 50 MHz in the HPS. Provision ~3x more bandwidth for Linux flash file systems on ARM cores to accelerate Uboot and Linux performance. -- Nios II software performance on HyperRAM and HyperFlash @ 150 MHz is highly competitive with 16-bit DDR3 @ 333 MHz, and is up to around 1.5x faster than 16-bit SDR SDRAM @ 100 MHz. Execute code directly from HyperFlash at similar levels of performance.
Free long term evaluation licenses of S/Labs HBMC IP with Avalon interface are available to all Intel customers for use on COTS and proprietary FPGA boards! -- Get started rapidly with one of our detailed step-by-step tutorials on our website. All tutorials include free trials of our IP.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Simulation model available for free upon request.
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Nios II HAL
IP-XACT Metadata included
Intel Edition of Modelsim
Y. Altera Board Name Intel Cyclone 10 LP Evaluation Kit. Devboards HyperMAX 25 and 50.
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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