Protocol IP - Designing For Multiple Industrial Ethernet Protocols
Block Diagram
Overview
Industrial Ethernet Implementation for Intel FPGAs - Simple and Efficient Solution for Designing Industrial Devices supporting Multiple Industrial Ethernet and Fieldbus Protocols As a leading supplier of industrial communication solutions Softing teamed-up with Intel and has generated an offering providing all the required hardware and firmware for implementing Industrial Ethernet and PROFIBUS field device functionality based on Intel FPGAs. This hardware and firmware bundle is named "Softing Protocol IP" and is available via Intel's worldwide sales channel as well as directly from Softing. Softing Protocol IP allows for easy implementation of Industrial Ethernet (PROFINET RT and IRT, EtherNet/IP, EtherCAT, Modbus TCP) and PROFIBUS slave devices based on Intel’s family of Cyclone FPGAs.
Features
- Simplified, No-Hassle Slave Device Implementation for Industrial Ethernet Protocols Plus PROFIBUS
- Ready-to-Use and Intel FPGA Tested Protocols Including FPGA IP and Software Protocol Stack running on Nios IIf
- Uniform Software API and Hardware Interface for All Protocols
- Flexible Integration Capabilities
- Short Time-to-Market
Device Utilization and Performance
PROFINET RT (2 ext. ETH ports, MRP enabled): switch IP (~4200 ALMs, 31 M10K), total subsystem (~7900ALMs, 72 M10K) PROFINET IRT (2 ext. ETH ports, MRPD, IO via DMA): switch IP (~8200 ALMs, 31 M10K), total subsystem (~12300ALMs, 91 M10K) EtherNet/IP (2 ext. ETH ports): switch IP (~4200 ALMs, 31 M10K), total subsystem (~7900ALMs, 72 M10K) Modbus/TCP (2 ext. ETH ports): switch IP (~4200 ALMs, 31 M10K), total subsystem (~7900ALMs, 72 M10K) EtherCAT (2 ext. ETH ports): ESC IP (~7900 ALMs, 9 M10K), total subsystem (~13000ALMs, 50 M10K) PROFIBUS: PB IP copre (~1900 aLMs, 10 M10K), total subsystem (~4600ALMs, 33 M10K)
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2020 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | ready to run QSYS subsystem including binary protocol software for Nios IIf |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | Y |
| Driver OS support | HAL (bare metal), Linux |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DK-DEV-5CEA7N, DK-DEV-5CSXC6N |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PROFINET conformance test |
| If yes, on which Altera device(s)? | Cyclone V E |
| If Yes, date performed | 02/13/2020 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.