MPEG-2 Encoder IP Core
Block Diagram

Overview
SOC provides a high-performance MPEG2 encoder IP core that supports all Intel FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one MPEG2 encoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2000 |
Latest version of Quartus supported | 17.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | PCB Reference Designs |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | Windows, Linux |
Implementation | |
User Interface | AXI; Avalon-MM |
IP-XACT Metadata included | Y |
Verification | |
Simulators supported | Modelsim |
Hardware validated | Y. Altera Board Name Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V |
Industry standard compliance testing performed | Y |
If yes, which test(s)? | MPEG Compliance |
If yes, on which Altera device(s)? | Cyclone V |
If Yes, date performed | 02/01/2010 |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | Y |
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