MPEG-2 Encoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

SOC provides a high-performance MPEG2 encoder IP core that supports all Intel FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one MPEG2 encoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs

Features

  • Zero latency (0.25ms)
  • Small silicon footprint (30k - 60kALMs)
  • Low power (less than 1w, for HD resolutions)
  • High video quality
  • User Control API

Device Utilization and Performance

Logic=60kALMs; Block RAM=5Mbits; DSP=310DSPs. Performance: Standard=MPEG2; Profiles=High; Bit-Rates=1-500Mbps; Resolution=HD and 4k; Chroma=4:2:2/4:2:0; Precision=8bits; Audio=MPEG-2 Layer-II; Latency=0.25ms.

Getting Started

SOC supplies plug-and-play evaluation kits for the MPEG2 encoder IP core. The product code for the evaluation kit is: EC-MPEG2-HD-KIT (for HD) and EC-MPEG2-4k-KIT (for 4k)

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
PCB Reference Designs
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportWindows, Linux
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedY
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V
Industry standard compliance testing performed
Y
If yes, which test(s)?MPEG Compliance
If yes, on which Altera device(s)?Cyclone V
If Yes, date performed
02/01/2010
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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