H.265/HEVC HD Encoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Stratix® IV, Stratix® V


SOC provides a high-performance H.265/HEVC HD encoder IP core that supports all Intel® FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.265 encoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.


  • Zero latency (0.5ms)
  • Small silicon footprint (90kALMs)
  • Low power (less than 3w, for HD resolutions)
  • High video quality
  • User Control API

Device Utilization and Performance

Logic=90kALMs; Block RAM=10Mbits; DSP=450DSPs. Performance: Standard=H.265/HEVC; Profiles=Main 12; Bit-Rates=1-500Mbps; Resolution=HD (1080p upto 120fps); Chroma=4:2:2/4:2:0; Precision=8/10/12 bits; Audio=AAC or MPEG-2 Layer-II; Latency=0.25ms.

Getting Started

SOC supplies plug-and-play evaluation kits for the H.265 HD encoder IP core. The product code for the evaluation kit is: EC-H265-HD-KIT

IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
PCB Reference Designs
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedY
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix V
Industry standard compliance testing performed
If yes, which test(s)?MPEG Compliance
If yes, on which Altera device(s)?Arria V
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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