H.264/AVC HD Encoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


SOC provides a high-performance H.264/AVC encoder IP core that supports all Intel FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.264 encoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.


  • Zero latency (0.25ms)
  • Small silicon footprint (30k - 60kALMs)
  • Low power (less than 1w, for HD resolutions
  • High video quality
  • User controllable API

Device Utilization and Performance

Logic=30-60kALMs; Block RAM=5Mbits; DSP=300DSPs. Performance: Standard=H.264/AVC (ISO/IEC14496-10); Profiles=High; Bit-Rates=1-500Mbps; Resolution=HD (1080p upto 240fps); Chroma=4:2:2/4:2:0; Precision=8/10 bits; Audio=AAC or MPEG-2 Layer-II; Latency=0.25ms.

Getting Started

SOC supplies plug-and-play evaluation kits for the H.264 encoder IP core (as well as for the encoder modules and chipsets). The product code for HD resolution encoder evaluation kit is: FMC-MCM-1000-H264-HD-EC SOC web page: http://www.soctechnologies.com/eval-kits/h264_hd_encoder_kit

IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
PCB Reference Designs
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportLimux
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedY
Simulators supportedModelsim
Hardware validated Y. Altera Board Name SOC Eval kits
Industry standard compliance testing performed
If yes, which test(s)?MEPG Compliance
If yes, on which Altera device(s)?Cyclone V
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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