H.264/AVC 8k Encoder IP Core
Block Diagram
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Requested Quartus report |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | WIndows, Linux |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim |
| Hardware validated | Y. Altera Board Name SOC PCIe-I-8K encoder eval kit |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | MPEG Compliance |
| If yes, on which Altera device(s)? | Arria 10 |
| If Yes, date performed | 03/14/2017 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.