H.264/AVC 4k Decoder IP Core
Block Diagram
Overview
SOC provides a high-performance H.264/AVC 4k decoder IP core that supports all Intel® FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.264 decoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2015 |
| Latest version of Quartus supported | 17.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | Y |
| Driver OS support | Windows |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim |
| Hardware validated | Y. Altera Board Name SOC Eval kits |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | MEPG Compliance |
| If yes, on which Altera device(s)? | Arria-10, Stratix-V |
| If Yes, date performed | 11/26/2015 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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