H.264/AVC 4k Decoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Stratix Series: Intel® Stratix® 10, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

SOC provides a high-performance H.264/AVC 4k decoder IP core that supports all Intel® FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.264 decoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.

Features

  • Zero latency (0.5ms)
  • Small silicon footprint (30k )
  • Low power (less than 1w, for 4k resolution)
  • 4:2:2/4:2:0; 8/10bits
  • AAC audio and UDP/IP+Ethernet available

Device Utilization and Performance

Logic=30kALMs; Block RAM=3Mbits; DSP=30DSPs. Performance: Standard=H.264/AVC (ISO/IEC14496-10); Profiles=High; Bit-Rates=4-500Mbps; Resolution=4k (3840x2160@30fps); Chroma=4:2:2/4:2:0; Precision=8/10 bits; Audio=AAC or MPEG-2 Layer-II; Latency=0.5ms.

Getting Started

SOC supplies plug-and-play evaluation kits for the H.264 4k encoder IP core. The product code for 4k resolution decoder evaluation kit is: DC-H264-4K-KIT SOC web page: https://www.soctechnologies.com/eval-kits/h264_4K_decoder_kit

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportWindows
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name SOC Eval kits
Industry standard compliance testing performed
Y
If yes, which test(s)?MEPG Compliance
If yes, on which Altera device(s)?Arria-10, Stratix-V
If Yes, date performed
11/26/2015
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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