True Random Number Generator (TRNG)
Block Diagram

Overview
The Random Number Generator (BA431) is an essential IP core for all FPGA and SoC designs that target cryptographically secured applications.The BA431 includes a True Random Generator (TRNG) as the source of entropy.The optional Deterministic Random Bit Generator (DRBG) can be provided with the core.The entropy source and theDRBG are designed for compliance with the NIST 800-90A and NIST 800-90B draft.It is easily portable to any Intel® FPGA device (including SoC). The IP core successfully passes NIST 800-22 and AIS31 test suites and has already passed FIPS 140-2 certification.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
N |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | Linux, bare-metal |
Implementation | |
User Interface | AXI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Mentor Graphics, Synopsys and Cadence |
Hardware validated | Y. Altera Board Name Cyclone V Development Kit, Socrates |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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