Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


We have a variety of IP cores: JPEG IP core with liabilities and achievements over 10 years since the birth of this trustworthy image file format worldwide, JPEG XR IP core in conformity of the format for the next generation. We also provide customers with services developing customized cores and customizing cores themselves. •JPEG Baseline IP Core   This IP core complies with the JPEG Baseline format and compresses/ decompresses still images. •JPEG EXTENDED IP Core   This IP core complies with the JPEG Extended DCT-based format and compresses/ decompresses the 8/ 12-bit images. •Lossless JPEG IP Core   This IP core complies with the Lossless JPEG format (ITU-T T.81 Annex H) and compresses/ decompresses still images without deterioration. •JPEG XR IP Core    The IP core complying with JPEG XR format (ISO/IEC 29199-2), a new still image compression/decompression format following JPEG and JPEG 2000.


  • •Shikino High-Tech's original algorithms have achieved high-speed, small-scale and power-thrifty processing.
  • •Several IP Core lineups which perform 1 to 32 times faster(Data/Rate) to meet each need (e.g., 8K4K resolution)

Device Utilization and Performance


Getting Started

For additional information, contact Shikino High-Tech Co., Ltd.

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS support-
User InterfaceOther: Original
IP-XACT Metadata includedN
Simulators supportedNC-Verilog
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If yes, which test(s)?JPEG Part2(ISO/IEC10918-2
If yes, on which Altera device(s)?Stratix IV
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  N

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