GigE Vision FPGA Core
Block Diagram

Overview
GigE Vision is a standard communication protocol for vision applications based on the well-known Ethernet technology. It allows easy interfacing between GigE Vision devices and PCs running TCP/IP protocol family. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the GigE Vision interface. Due to the speed of GigE Vision, especially at speeds higher than 1 Gb/s, senders and receivers require a fast FPGA-based implementation of the embedded GigE core. GigE Vision cores compatible with Xilinx 7 Series devices (and higher) and Intel/Altera Cyclone V devices (and higher).
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2008 |
Latest version of Quartus supported | 17.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | AXI based frame buffer, MAC core |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | Linux/Win/OSX |
Implementation | |
User Interface | AXI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim |
Hardware validated | Y. Altera Board Name INK, MVDK, Arria V GX Starter |
Industry standard compliance testing performed | Y |
If yes, which test(s)? | GEV by visiononline.org |
If yes, on which Altera device(s)? | C IV/V, Arria V/10 |
If Yes, date performed | 11/09/2018 |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | Y |
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