WalnutDSA Signature Verification IP Core for Intel MAX 10

Block Diagram

Solution Type: Qsys Component

End Market: Automotive, Industrial, Medical, Military, Wireline

Evaluation Method: Source Code

Technology: Basic Functions: Miscellaneous

MAX Series: Intel® MAX® 10

Overview

A digital signature verification function that is implemented partially in Nios II software and partially in FPGA programmable logic. The function is used for secure boot and secure firmware updates, and may also be used to validate signatures made over messages and certificates. For evaluation purposes, SecureRF provides a terminal-based signing application for Linux or Windows to enable customers to generate WalnutDSA signatures. The user specifies a message file (the file that is being signed), the private key of the trusted signing party, and the output file that the signature will be stored in. For production, SecureRF offers HSM-based key generation and signing appliances to Walnut customers.

Features

  • •\tPerforms signature verification in under 5ms
  • •\tAlgorithm is resistant to all known Quantum Computing attacks
  • •\tVery little ROM, RAM, and logic utilization required

Device Utilization and Performance

Logic Cells = 10941 Dedicated Logic Registers = 4885 Memory Bits = 152448 M9K’s = 40

Getting Started

Contact SecureRF Corp. for Quick-start guide,

IP Quality Metrics

Basic
Year IP was first released2018
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Detailed protocol description
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name On Intel MAX 10 evaluation board
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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