WalnutDSA Signature Verification IP Core for Intel MAX 10
Block Diagram
Overview
A digital signature verification function that is implemented partially in Nios II software and partially in FPGA programmable logic. The function is used for secure boot and secure firmware updates, and may also be used to validate signatures made over messages and certificates. For evaluation purposes, SecureRF provides a terminal-based signing application for Linux or Windows to enable customers to generate WalnutDSA signatures. The user specifies a message file (the file that is being signed), the private key of the trusted signing party, and the output file that the signature will be stored in. For production, SecureRF offers HSM-based key generation and signing appliances to Walnut customers.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2018 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Detailed protocol description |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name On Intel MAX 10 evaluation board |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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