End Market: Automotive, Consumer, Industrial, Medical, Military, Wireless
Evaluation Method: Source Code
Technology:Basic Functions: Miscellaneous
Cyclone Series: Cyclone® V SoC
A digital signature verification function that is implemented partially in HPS software and partially in FPGA programmable logic. The function is used for secure boot and secure firmware updates, and may also be used to validate signatures made over messages and certificates.
For evaluation purposes, SecureRF provides a terminal-based signing application for Linux or Windows to enable customers to generate WalnutDSA signatures. The user specifies a message file (the file that is being signed), the private key of the trusted signing party, and the output file that the signature will be stored in. For production, SecureRF offers HSM-based key generation and signing appliances to Walnut customers.
Performs signature verification in under 1ms
Algorithm is resistant to all known Quantum Computing attacks
Very little ROM, RAM, and logic utilization required
Device Utilization and Performance
On CV SoC device (5CSEBA6U2317NDK). Contact SecureRF Corp. for other FPGA benchmarks.
10K Memory block type: 28 (5%)
Block memory bits: 134,912 (2%)
Dedicated logic registers: 4,612 (5%)
ALM's: 4,040 (9.6%)
Performs signature verification in under 1ms.
Contact SecureRF Corp. for Quick-start guide
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Detailed protocol description
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Terasic DE10-Nano Cyclone V SoC board
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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