Arria 10 SoC FMC Full Height PCIe board
Board Image

Block Diagram

Overview
Designing for high performance serial transceiver applications using series 10 SoC Intel® FPGAs Intel® Arria® 10 SoC 660 KLEs in F34 package compliant 660 KLEs Hardware, software design tools, IP, and pre-verified reference designs. PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3) Advanced memory interface with DDR3 on board Memory up to 4GB Develop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII​) Implement Video display applications with Display output port (up to 5.4Gbit/s) The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only ( +vadj) •160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V) •4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS •10 XCVR (up to: 14.2 Gb/s)* * Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s
Development Kit Software Contents
- Board support package (BSP) (upon request)
Support Document
File Name | Description | Version |
---|---|---|
doc-us-dsnbk-174-4905543112590-ace-rev-3.pdf | Flyer Alaric | 4.3 |
Board Quality Metrics
Basic |
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Latest version of Quartus supported | 15.1 |
Required Collateral Available | |
User Guide | Y |
Board Schematics | N |
Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 0 |
Parts per Million (PPM) | 0 |
Board Policy | |
Return Material Authorization (RMA) Policy | Available on request through REFLEX CES support web site. |
Compliance | |
RoHS Compliant | Y |
CE Compliant | Y. Yes |
Conflict Mineral Policy Compliant |
Y |
Test Plan Summary | |
ReFLEX CES provides all the files required to enable test interfaces or help the user to start his own design. |
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Additional Compliance | |
ISO 9000 & 9001 |
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