Designing for high performance serial transceiver applications using series 10 SoC Intel� FPGAsIntel� Arria� 10 SoC 660 KLEs in F34 package compliant 660 KLEsHardware, software design tools, IP, and pre-verified reference designs.PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3)Advanced memory interface with DDR3 on board Memory up to 4GBDevelop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII)Implement Video display applications with Display output port (up to 5.4Gbit/s)The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front endThe FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only ( +vadj)�160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)�4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS�10 XCVR (up to: 14.2 Gb/s)* * Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s
Available on request through REFLEX CES support web site.
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Test Plan Summary
ReFLEX CES provides all the files required to enable test interfaces or help the user to start his own design.
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